WO/2014/082660

Abstract

The present invention includes any kind of unit cell for collecting charges from pixel, an under-pixel comparator circuit to convert analog data to digital data, several counters to store the digital data for most significant bits (MSBs) and least signiciant bits (LSBs), a control circuit driving multiplexers and switches for proper TDI operation, a digital-to-analog converter (DAC) to drive comparator for determination of LSBs.

Type
Publication
Pixel Level Digital Implementation of Time Delay Integration Algorithm for Low Noise, High Dynamic Range and Low Power Readout Integrated Circuits